As data-driven applications become more prevalent, the demand for solutions that can keep pace with lightning-fast data processing grows. Wolley NVMe-over-CXL, a breakthrough architecture, aims at redefining the memory computing paradigm over storage.

But why should an NVMe SSD embrace a CXL interface in replace of the conventional PCIe interface? Let us explore the key factors that make things clear.

In traditional computing schemes, data retrieval from storage involves a series of steps, including traversing the NVMe protocol, relying on the NVMe driver, and applying software cache techniques like page caching. However, when the block data (typically 4KB in size) reaches the host, only a small fraction of it is actually required for computation. This mismatch between the amount of data retrieval and the data needed for computation can lead to serious inefficiencies.

There are some solutions or architectures trying to overcome this problem. One example is computational storage. The core idea is to convey computing instructions directly from the host to the storage device via NVMe. As the computations are performed on the device itself, only the resulting data, which is often smaller than the original block data, is returned to the host through the NVMe interface again.

In our proposal of NVMe-over-CXL, the SSD functions still work as a typical NVMe SSD and can still access block data via NVMe commands. One key invention is the integration of a DRAM on the device side. The purpose is to make the device DRAM a staging area of data. One major operation is to make the destination of the block data falling on the device DRAM. As a matter of that, the most crucial step is that the host, utilizing CXL.mem, can then selectively retrieve the necessary bytes from the block data, thus avoiding the transfer of huge block data between the host and the device. This efficient architecture significantly reduces latency and complexity.

CXL opens up new possibilities, especially for storage. In traditional NVMe setups, all block data is moved to the host memory, leading to bottlenecks due to the complexity of NVMe protocols and the burden of heavy block-based storage software management. By having a staging memory on the device side, NVMe over CXL allows the host to access data in a memory mode, streamlining data transfers and boosting overall efficiency.