Phone：03-5711161
Connect Your Core To The CXL World
公司沿革
History
Milestones
2016/09
後台備註文字（前台不顯示，可隨時刪除）：
- 圖片的class有設定最大寬度450px，如果需要改成滿版圖片，刪除該class即可（max450w）。
- 圖標取自素材網flaticon，如果有其他希望增修的icon，可再與我們聯繫。
Wolley Founded
Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.
2017/12
First DRAM-less SCM Controller IP
Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.
2019/03
Wolley Tableless Wear-leveling Patent Granted
Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.
2021/11
Series B Funding Round Completed
Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.
2022
CXL 1.0 IP
Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.
2023
CXL 2.0 IP & CXL Native Memory
Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.
2024
CXL 3.0 IP & NVMe-over-CXL
Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.