Job description

1. SoC top/sub-system architecture planning and  design integration.
2. SoC design implementation from logic synthesis to physical implementation.
3. Work with multiple teams and drive RTL to GDS flow.

Requirement

1. Familiar with Verilog HDL and digital IC design flow, including RTL sign-off, Synthesis, LEC, STA, timing-signoff.
2. Better to have DFT/ATPG and MBIST knowledge.
3. Better to have FPGA implementation experience.