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Designer
Design Verification
Job description
- Design verification with SystemVerilog/UVM, C/C++
- Integration test environment with VIP
- Develop checker and scoreboard.
- Verify design with SystemVerilog assertion.
- Test plan for a verification task.
- Architecture design and RTL implementation
Requirement
- Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming.
- Better to have SoC design and bus concept.