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CXL Controller IP
Technology
CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable designfor ASIC and FPGA implementations. It maintains backward compatibility with CXL 2.0and 1.1 and forms a complete solution when combined with other vendor’s PHY IP. Thecontroller supports a variety of configurations including Root Port, Endpoint, and Switchmodes, making it ideal for integration across SoC platforms, data centers, and AI/MLaccelerators. The controller is verified in emulation, FPGA, and silicon environments withproven interoperability.
Key Features
- CXL 3 compliant at 64 GT/s; backward compatible with CXL 2.0/1.1
- Integrated support for CXL.io, CXL.cache, and CXL.mem protocols
- Suport CXL.cachemen Lower Data-Link Layer user interface and Higher Data-LinkLayer user interface
- Support Root Port, Endpoint and Switch Upstream/Downstream
- PIPE 6.x-compliant PHY interface
- Parallel TLP/DLLP engines for high throughput and low latency
- Technology-independent soft IP cores for FPGA and ASIC
- Customizable datapath widths
- Configurable pipeline to meet different technology
Benefits
- Easy-to-integrate plug-and-play IP cores with rich documentation
- Support for both FPGA and ASIC implementations for flexible deployment
- Scalable architecture supporting various widths and modes to fit exact use cases
- Extensive verification on real hardware platforms ensures faster time-to-market
- Verified against major VIPs and hardware platforms (e.g., Intel Granite Rapids)
Applications
Network Interface Cards (NICs); Memory pooling and expansion solutions; AI/MLacceleration engines; High-performance computing (HPC) SoCs; Server-class and datacenter infrastructure