Customizability

• Configurable controller modes: Device Dual Mode (Root Port or Endpoint), Switch Dual Mode (Switch Downstream Port or Switch Upstream Port) supported
• Customizable 256/512/1024 bits data path

Supportability

• CXL 3.0 at 64 GT/s (backward compatible to CXL 2.0 and 1.1), in Type 1/2/3 devices with CXL.io/CXL.cache/CXL.mem
• Compliant with PIPE 6.x (32- / 64-bit) specification
• Supports PCIe 6.0, PCIe 5.0, PCIe 4.0, PCIe 3.1/3.0
• Supports x16, x8, x4, x2, x1 link at Gen5, Gen4, Gen3, Gen2, Gen1 speeds
• Single-Root I/O Virtualization (SR-IOV) Specification
• Port Bifurcation

Additional Features

• CXL/PCIe IDE
• Advanced Error Reporting (AER)
• Optimized Buffer Flush/Fill mechanism (OBFF)
• TLP Processing Hint (TPH)
• Latency Tolerance Reporting (LTR)
• ID based Ordering (IDO)